1. Field of the Invention
This invention relates to a three-dimensional warp-resistant integrated circuit module. In particular, the invention relates to thin layers of material mounted to selected integrated circuit packages within the module to balance moments of inertia around a selected neutral thermodynamic axis within the module to prevent thermal and mechanical warping of the module.
2. Discussion of the Related Technology
In an attempt to configure electronic systems in ever smaller packages, new methods and apparatus comprising three-dimensional stacked integrated circuit packages have been developed as more fully described in U.S. Pat. No. 5,420,751, entitled "Ultra High Density Integrated Circuit Packages," and U.S. Pat. No. 5,367,766, entitled "Ultra High Density Integrated Circuit Packages Method," both having the common assignee of the present invention and incorporated herein by reference for all purposes. U.S. patent application Ser. No. 07/990,334, filed Dec. 11, 1992, now allowed, entitled "High Density Lead-on-Package," assigned to the common assignee of the present invention and incorporated herein, discloses the use of a stiffener to prevent the mechanical warping of a thin integrated circuit package. Methods and apparatus for controlling thermally induced warpage are discussed in U.S. Pat. No. 5,369,056, entitled "Warp-Resistant Ultra Thin Package" and in U.S. Pat. No. 5,369,058, entitled "Warp-Resistant Ultra Thin Packages Method," both assigned to the common assignee of the present invention and incorporated herein for all purposes.
In contrast to such prior art technology, the present invention includes a three-dimensional warp-resistant integrated circuit module that is thermally and mechanically balanced to prevent ultra-thin profile packages comprising the module from warping.